Knowledge grounded
Retrieve from hardware design references, official documentation, textbooks, and engineering discussions before generating an answer.
AI-powered chip engineers
Designing the next generation of silicon intelligence.
AICE is building an AI orchestration layer for chip design—helping engineers connect knowledge, tools, and specialized agents.
The platform
An AI engineer for the complexity of chip design.
Chip design is too complex, expensive, and context-heavy for isolated tools to solve alone. AICE is designed to understand the engineering context, coordinate specialized agents, and preserve the knowledge behind each decision.
Engineers stay in control while AICE helps connect requirements, RTL, verification, tools, and design iteration into a more coherent workflow.
How AICE fits
From design intent to validated output.
AICE sits alongside the engineer as a planning and knowledge layer across the front-end design flow. It helps teams ask better questions, choose the right support, and keep project context available for the next iteration.
Research & approach
Domain knowledge, grounded answers, human judgment.
Workflow aware
Reason about the workflow and available agents a team already uses instead of forcing a replacement process.
Engineer led
Keep engineers responsible for design intent, tradeoffs, verification, and final decisions while reducing repetitive work.
Roadmap
Building capability in deliberate stages.
V1 · Current
Search + Plan
Grounded chip-design knowledge, answers, and workflow planning.V2 · Next
Execute
Run plans through external tools and return tool-backed results.V3 · Future
Orchestrate
Coordinate specialized agents natively across the design workflow.Meet the Team
Zahin Ibnat
Founder and CEO
Mark Tehranipoor
Founder and Advisor
Engineering Team
Jyothi Nandhan Repaka
AI/ML Engineer
Roop Sai Charan Kothamasu
Engineering Team
Atish Maragur
Chip Design Engineer
Advisors
Jay Lewis
Technical Advisor
Sazadur Rahman
Technical Advisor
Yatin Hoskote
Strategic Advisor
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